The microcontroller controls and generating a similarity score for the input and template monitors all activities that take place in the card, in the same prints.
Generally, the similarity score is normalized in the way as current smart cards, but the application is now range [0,1] meaning the closer the score is to 1, the more developed by means of hardware-software co-design certain is the recognition system that both fingerprints come techniques. After similarity analysis, the comparison of the resultant match score with a certain threshold will state whether both original fingerprints are generated or not from the same finger.
Many methods for matching two fingerprint images have been presented in literature [1]. Among these three groups, minutiae-based is the most widely used technique due to its good performance with less computational costs processing time and memory needs than other techniques.
Matching two fingerprints in Figure 2. Physical platform developed in this work. Three main minutiae-based representations becomes a point pattern- components are used: a SoC device, an Eeprom and a fingerprint sensor.
Several algorithms have been proposed in the last match on card system making use of the proposed decades to efficiently match two fingerprint minutiae sets. With this new configuration, specific Among them, authors have selected those dealing with coprocessors can be synthesized into the FPGA to speed up structural analysis. The proposed algorithm is abstracted from [13], [14]. It the transformation matrix 5 to get the alignment of both uses both local and global structures of minutiae to perform fingerprint images.
Y As result of the global analysis stage, those overlapped areas between both prints are identified. For the purpose because generally ridge endings and bifurcations are difficult of this paper, it is assumed that template and input to be distinguished when low quality fingerprint impressions minutiae sets have been already sent to the smart card are present.
Moreover, the CPU is in allows calculating the spatial difference translation and charge of reading the template minutiae, previously rotation that exists between both fingerprint minutiae sets, saved in the EEPROM memory. These three parameters are used in are set up in RAM memory. Table 1shows the list of tasks system just before starting the matching process. Once template and input minutiae sets are aligned, the V.
The final performance reached by the application is shown on table 2 and figure 5. Application flow diagram. FPGA performance incorporates additional benefits in terms of increasing processing power. Although in most of current systems those computationally expensive tasks take place out of the smart card, the introduction of this novel architecture makes feasible to embed additional tasks such as fingerprint acquisition or feature extraction processes inside the card.
Thus, this novel architecture opens the door to the next smart card generation: authentication on card systems, as depicted on figure 6, where a significant security improvement of the overall personal authentication system against external attacks can result.
Jain, R. Bolle, S. Sanchez-Reillo, L. Mengibar-Pozo, C. Prototype board developed in this work. Trichina, M. Bucci, D. De Seta, R. Current smart card technology deals with limited [4] T.
Bourlai, K. Messer, J. Some smart cards additionally incorporate Pattern Recognition, Vol. Sanchez-Reillo, A. Polski English Login or register account. Hardware-software co-design of an iris recognition algorithm.
Abstract This study describes the implementation of an iris recognition algorithm based on hardware-software co-design. The system architecture consists of a general-purpose bit microprocessor and several slave coprocessors that accelerate the most intensive calculations.
The whole iris recognition algorithm has been implemented on a low-cost Spartan 3 FPGA, achieving significant reduction in execution time when compared with a conventional software-based application.
Experimental results show that with a clock speed of MHz, an IrisCode is obtained in ms from an image of pixels, which is just of the total time needed by a software solution running on the same microprocessor embedded in the architecture.
Authors Close. Assign yourself or invite other person as author. It allow to create list of users contirbution. Assignment does not change access privileges to resource content. Wrong email address. You're going to remove this assignment. IEEE 85 9 , — Signal Process. Avey, J. Al-Mamory, H. Babylon Univ.
Pure Appl. Imaging 24 4 , 1— 12 Zhang, S. In: Chinese Conference on Biometric Recognition, vol. LNCS, pp. Ali, M. Bailey, D. Wiley, Hoboken Book Google Scholar.
Rosenfeld, A. ACM 13 4 , — Klaiber, M. MMU iris database Accessed Dec Chinese Academy of Sciences. Bowyer, K. Phillips, P. Pattern Anal. In: Biometrics: Theory, Applications and Systems Masek, L.
IET Image Process. Rakvic, R. Forensics Secur. Ng, R. Giacometto, F.
0コメント